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74abt16501a 74abth16501a 18-bit universal bus transceiver (3-state) product specification supersedes data of 1997 jun 12 ic23 data handbook 1998 feb 27 integrated circuits
philips semiconductors product specification 74abt16501a 74abth16501a 18-bit universal bus transceiver (3-state) 2 1998 feb 27 853-1788 19027 features ? 18-bit bidirectional bus interface ? 3-state buffers ? output capability: +64ma/-32ma ? ttl input and output switching levels ? 74abth16501a incorporates bus-hold data inputs which eliminate the need for external pull-up resistors to hold unused inputs ? live insertion/extraction permitted ? power-up reset ? power-up 3-state ? positive edge-triggered clock inputs ? latch-up protection exceeds 500ma per jedec std 17 ? esd protection exceeds 2000v per mil std 883 method 3015 and 200v per machine model ? flexible operation permits 18 embedded d-type latches or flip-flops to operate in clocked, transparent, and latched modes. description the 74abt16501a high-performance bicmos device combines low static and dynamic power dissipation with high speed and high output drive. this device is an 18-bit universal transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. data flow in each direction is controlled by output enable (oeab and oeba ), latch enable (leab and leba), and clock (cpab and cpba) inputs. for a-to-b data flow, the device operates in the transparent mode when leab is high. when leab is low, the a data is latched if cpab is held at a high or low logic level. if leab is low, the a-bus data is stored in the latch/flip-flop on the low-to-high transition of cpab. when oeab is high, the outputs are active. when oeab is low, the outputs are in the high-impedance state. data flow for b-to-a is similar to that of a-to-b but uses oeba , leba and cpba. the output enables are complimentary (oeab is active high, and oeba is active low). active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. two options are available, 74abt16501a which does not have the bus-hold feature and 74abth16501a which incorporates the bus-hold feature. quick reference data symbol parameter conditions t amb = 25 c; gnd = 0v typical unit t plh t phl propagation delay an to bn or bn to an c l = 50pf; v cc = 5v 2.2 1.8 ns c in input capacitance (control pins) v i = 0v or v cc 3 pf c i/o i/o pin capacitance outputs disabled; v i/o = 0v or v cc 7 pf i ccz quiescent su pp ly current outputs disabled; v cc = 5.5v 500 m a i ccl q u iescent s u ppl y c u rrent outputs low; v cc = 5.5v 9 ma ordering information packages temperature range outside north america north america dwg number 56-pin plastic ssop type iii 40 c to +85 c 74abt16501a dl bt16501a dl sot371-1 56-pin plastic tssop type ii 40 c to +85 c 74abt16501a dgg bt16501a dgg sot364-1 56-pin plastic ssop type iii 40 c to +85 c 74abth16501a dl bh16501a dl sot371-1 56-pin plastic tssop type ii 40 c to +85 c 74abth16501a dgg bh16501a dgg sot364-1
philips semiconductors product specification 74abt16501a 74abth16501a 18-bit universal bus transceiver (3-state) 1998 feb 27 3 logic symbol 3 5 6 8 9 10 12 13 14 15 16 17 19 20 21 23 24 26 a0 a1 a2 a3 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a4 b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15 b16 b17 54 52 51 49 47 45 44 43 42 41 40 38 37 36 34 33 31 48 1 2 55 27 28 30 cpba leba oeba cpab leab oeab sa00127 pin description pin number symbol name and function 1 oeab a-to-b output enable input 27 oeba b-to-a output enable input (active low) 2, 28 leab/leba a-to-b/b-to-a latch enable input 55,30 cpab/ cpba a-to-b/b-to-a clock input (active rising edge) 3, 5, 6, 8, 9, 10, 12, 13, 14, 15, 16, 17, 19, 20, 21, 23, 24, 26 a0-a17 data inputs/outputs (a side) 54, 52, 51, 49, 48, 47, 45, 44, 43, 42, 41, 40, 38, 37, 36, 34, 33, 31 b0-b17 data inputs/outputs (b side) 4, 11, 18, 25, 32, 39, 46, 53 gnd ground (0v) 7, 22, 35, 50 v cc positive supply voltage pin configuration gnd gnd gnd gnd leab oeab gnd v cc v cc gnd gnd v cc v cc gnd gnd gnd leba oeba 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 cpab b0 b2 b1 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15 b16 b17 cpba sa00128
philips semiconductors product specification 74abt16501a 74abth16501a 18-bit universal bus transceiver (3-state) 1998 feb 27 4 logic symbol (ieee/iec) en1 2c3 c3 g2 en4 5c6 c6 g5 3d 1 1 416d 1 55 2 27 30 28 3 5 6 8 9 10 12 13 14 15 16 17 19 20 21 23 24 26 54 52 51 49 48 47 45 44 43 42 41 40 38 37 36 34 33 31 sa00129 oeab cpab leab oeba cpba leba a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15 b16 b17
philips semiconductors product specification 74abt16501a 74abth16501a 18-bit universal bus transceiver (3-state) 1998 feb 27 5 function table inputs internal registers outputs operating mode oeab leab cpab an r eg i s t ers bn operating mode l h x x x z disabled l x h h z disabled latch data l x i l z disabled , latch data l l h or l x nc z disabled, hold data l l h h z disabled clock data l l i l z disabled , clock data h h x h h h trans p arent h h x l l l trans arent h x h h h latch data & dis p lay h x i l l latch data & dis lay h l h h h clock data & dis p lay h l i l l clock data & dis lay h l h or l x h h hold data & dis p lay h l h or l x l l hold data & dis lay note: a-to-b data flow is shown; b-to-a flow is similar but uses oeba , leba, and cpba. h = high voltage level h = high voltage level one set-up time prior to the enable or clock transition l = low voltage level i = low voltage level one set-up time prior to the enable or clock transition nc= no change x = don't care z = high impedance ooffo state = high-to-low enable or clock transition = low-to-high clock transition
philips semiconductors product specification 74abt16501a 74abth16501a 18-bit universal bus transceiver (3-state) 1998 feb 27 6 logic diagram c1 id id c1 oeab leab clkab clkba oeba leba 1 2 55 30 28 27 54 b1 to 17 other channels a1 3 clk clk sw00235
philips semiconductors product specification 74abt16501a 74abth16501a 18-bit universal bus transceiver (3-state) 1998 feb 27 7 absolute maximum ratings 1, 2 symbol parameter conditions rating unit v cc dc supply voltage 0.5 to +7.0 v i ik dc input diode current v i < 0 18 ma v i dc input voltage 3 1.2 to +7.0 v i ok dc output diode current v o < 0 50 ma v out dc output voltage 3 output in off or high state 0.5 to +5.5 v i o dc out p ut current output in low state 128 ma i out dc o u tp u t c u rrent output in high state 64 ma t stg storage temperature range 65 to +150 c notes: 1. stresses beyond those listed may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under arecommended operating conditionso is not implied. exposur e to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. the performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create ju nction temperatures which are detrimental to reliability. the maximum junction temperature of this integrated circuit should not excee d 150 c. 3. the input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. recommended operating conditions symbol parameter limits unit symbol parameter min max unit v cc dc supply voltage 4.5 5.5 v v i input voltage 0 v cc v v ih high-level input voltage 2.0 v v il input voltage 0.8 v i oh high-level output current 32 ma i ol low-level output current 64 ma d t/ d v input transition rise or fall rate; outputs enabled 10 ns/v t amb operating free-air temperature range 40 +85 c
philips semiconductors product specification 74abt16501a 74abth16501a 18-bit universal bus transceiver (3-state) 1998 feb 27 8 dc electrical characteristics limits symbol parameter test conditions t amb = +25 c t amb = 40 c to +85 c unit min typ max min max v ik input clamp voltage v cc = 4.5v; i ik = 18ma 0.8 1.2 1.2 v v cc = 4.5v; i oh = 3ma; v i = v il or v ih 2.5 2.9 2.5 v v oh high-level output voltage v cc = 5.0v; i oh = 3ma; v i = v il or v ih 3.0 4.0 3.0 v v cc = 4.5v; i oh = 32ma; v i = v il or v ih 2.0 2.4 2.0 v v ol low-level output voltage v cc = 4.5v; i ol = 64ma; v i = v il or v ih 0.35 0.55 0.55 v v rst power-up output voltage 3 v cc = 5.5v; i o = 1ma; v i = gnd or v cc 0.13 0.55 0.55 v i i input leakage current v cc = 5.5v; v i = gnd or 5.5v control pins 0.01 1.0 1.0 m a b h ld ta db v cc = 4.5v; v i = 0.8v 35 35 i hold bus hold current a and b ports 5 74abth16501a v cc = 4.5v; v i = 2.0v 75 75 m a v cc = 5.5v; v i = 0 to 5.5v 800 i off power-off leakage current v cc = 0.0v; v o or v i 4.5v 2 100 100 m a i pu/pd power-up/down 3-state output current 4 v cc = 2.1v; v o = 0.0v or v cc ; v i = gnd or v cc ; v oe = don't care 2 50 50 m a i ih + i ozh 3-state output high current v cc = 5.5v; v o = 5.5v; v i = v il or v ih 1.0 10 10 m a i il + i ozl 3-state output low current v cc = 5.5v; v o = 0.0v; v i = v il or v ih 1.0 10 10 m a i cex output high leakage current v cc = 5.5v; v o = 5.5v; v i = gnd or v cc 2.0 50 50 m a i o output current 1 v cc = 5.5v; v o = 2.5v 50 80 180 50 180 ma i cch v cc = 5.5v; outputs high, v i = gnd or v cc 0.5 2 2 ma i ccl quiescent supply current v cc = 5.5v; outputs low, v i = gnd or v cc 9 19 19 ma i ccz v cc = 5.5v; outputs 3state; v i = gnd or v cc 0.5 2 2 ma d i cc additional supply current per input pin 2 74abt16501a v cc = 5.5v; one input at 3.4v, other inputs at v cc or gnd 5.0 50 50 m a d i cc additional supply current per input pin 2 74abth16501a v cc = 5.5v; one input at 3.4v, other inputs at v cc or gnd 200 500 500 m a notes: 1. not more than one output should be tested at a time, and the duration of the test should not exceed one second. 2. this is the increase in supply current for each input at 3.4v. 3. for valid test results, data must not be loaded into the flip-flops (or latches) after applying the power. 4. this parameter is valid for any v cc between 0v and 2.1v, with a transition time of up to 10msec. from v cc = 2.1v to v cc = 5v 10% a transition time of up to 100 m sec is permitted. 5. this is the bus hold overdrive current required to force the input to the opposite logic state.
philips semiconductors product specification 74abt16501a 74abth16501a 18-bit universal bus transceiver (3-state) 1998 feb 27 9 ac characteristics gnd = 0v, t r = t f = 2.5ns, c l = 50pf, r l = 500 w limits symbol parameter waveform t amb = +25 o c v cc = +5.0v t amb = 40 to +85 o c v cc = +5.0v 0.5v unit min typ max min max f max maximum clock frequency 1 150 225 150 mhz t plh t phl propagation delay an to bn or bn to an 2 1.0 1.0 2.2 1.8 3.0 2.5 1.0 1.0 3.5 3.0 ns t plh t phl propagation delay leab to bn or leba to an 3 1.5 1.4 3.2 2.9 4.3 3.8 1.5 1.4 5.0 4.2 ns t plh t phl propagation delay cpab to bn or cpba to an 1 1.6 1.4 3.5 2.9 4.5 3.8 1.6 1.4 5.0 4.2 ns t pzh t pzl output enable time to high and low level 5 6 1.1 1.0 3.0 2.4 4.0 3.4 1.1 1.0 4.7 3.9 ns t phz t plz output disable time from high and low level 5 6 1.3 1.0 3.3 2.4 4.3 3.4 1.3 1.0 5.3 3.9 ns ac setup requirements gnd = 0v, t r = t f = 2.5ns, c l = 50pf, r l = 500 w limits symbol parameter waveform t amb = +25 o c v cc = +5.0v t amb = 40 to +85 o c v cc = +5.0v 0.5v unit min typ min t s (h) t s (l) setup time, high or low an to cpab or bn to cpba 4 2.0 2.0 0.5 0.5 2.0 2.0 ns t h (h) t h (l) hold time, high or low an to cpab or bn to cpba 4 0.7 0.7 0.5 0.5 0.7 0.7 ns t s (h) t s (l) setup time, high or low an to leab or bn to leba 4 2.0 2.0 0.5 0.4 2.0 2.0 ns t h (h) t h (l) hold time high or low an to leab or bn to leba 4 0.7 0.7 0.4 0.5 0.7 0.7 ns t w pulse width, high or low cpab or cpba 1 3 1.9 3 ns t w (h) pulse width, high leab or leba 3 3 1.2 3 ns ac waveforms v m = 1.5v, v in = gnd to 3.0v t phl t plh v m v m v m v m t w (l) 1/f max cpba or cpab an or bn t w (h) sa00131 waveform 1. propagation delay, clock input to output, clock pulse width, and maximum clock frequency v ol t plh v oh an or bn an or bn v m v m t phl v m v m sa00132 waveform 2. propagation delay, transparent mode
philips semiconductors product specification 74abt16501a 74abth16501a 18-bit universal bus transceiver (3-state) 1998 feb 27 10 ac waveforms (continued) v m = 1.5v, v in = gnd to 3.0v t plh t phl t w (h) v m v m v m v m v m leab or leba an or bn v oh v ol sa00133 waveform 3. propagation delay, enable to output, and enable pulse width v m v m v m v m v m v m an or bn cpab or cpba, leab or leba t s (h) t h (h) t s (l) t h (l) sa00134 note: the shaded areas indicate when the input is permitted to change for predictable output performance. waveform 4. data setup and hold times oeba oeab an or bn v m v m v m t pzh t phz v oh v oh 0.3v sa00135 waveform 5. 3-state output enable time to high level and output disable time from high level v ol oeba oeab v m v m t pzl t plz v m an or bn v ol +0.3v sa00136 waveform 6. 3-state output enable time to low level and output disable time from low level test circuit and waveforms pulse generator r t v in d.u.t. v out r l v cc r l 7.0v test circuit for 3-state outputs v m v m t w amp (v) negative pulse 10% 10% 90% 90% 0v v m v m t w amp (v) positive pulse 90% 90% 10% 10% 0v t thl (t f ) t tlh (t r )t thl (t f ) t tlh (t r ) v m = 1.5v input pulse definition definitions r l = load resistor; see ac characteristics for value. c l = load capacitance includes jig and probe capacitance; see ac characteristics for value. r t = termination resistance should be equal to z out of pulse generators. input pulse requirements family amplitude rep. rate t w t r t f 74abt/h16 3.0v 1mhz 500ns 2.5ns 2.5ns switch position test switch t plz closed t pzl closed all other open sa00018 c l
philips semiconductors product specification 74abt16501a 74abth16501a 18-bit universal bus transceiver (3-state) 1998 feb 27 11 ssop56: plastic shrink small outline package; 56 leads; body width 7.5 mm sot371-1
philips semiconductors product specification 74abt16501a 74abth16501a 18-bit universal bus transceiver (3-state) 1998 feb 27 12 tssop56: plastic thin shrink small outline package; 56 leads; body width 6.1mm sot364-1
philips semiconductors product specification 74abt16501a 74abth16501a yyyy mmm dd 13 definitions short-form specification e the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition e limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the dev ice at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limi ting values for extended periods may affect device reliability. application information e applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. disclaimers life support e these products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use i n such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes e philips semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. philips semiconductors ass umes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or m ask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right in fringement, unless otherwise specified. philips semiconductors 811 east arques avenue p.o. box 3409 sunnyvale, california 940883409 telephone 800-234-7381 ? copyright philips electronics north america corporation 1998 all rights reserved. printed in u.s.a. print code date of release: 05-96 document order number: 9397-750-03494
data sheet status objective specification preliminary specification product specification product status development qualification production definition [1] this data sheet contains the design target or goal specifications for product development. specification may change in any manner without notice. this data sheet contains preliminary data, and supplementary data will be published at a later date. philips semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. this data sheet contains final specifications. philips semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. data sheet status [1] please consult the most recently issued datasheet before initiating or completing a design.

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